SC Alert: Host System has Reset NOTICE: Keyswitch set to diagnostic position. @(#)OBP 4.18.10 2006/03/03 13:59 Sun Fire V210/V240,Netra 210/240 Clearing TLBs Power-On Reset Executing Power On Self Test 0> 0>@(#) Sun Fire[TM] V210/V240, Netra[TM] 210/240 POST 4.18.10 2006/03/03 14:19 /export/delivery/delivery/4.18/4.18.10/post4.18.0/Fiesta/enxs/integrated (root) 0>Copyright © 2006 Sun Microsystems, Inc. All rights reserved SUN PROPRIETARY/CONFIDENTIAL. Use is subject to license terms. 0>Hard Powerup RST thru SW 0>OBP->POST Call with %o0=00001000.01014000. 0>Diag level set to MAX. 0>Verbosity level set to MAX. 0>MFG scrpt mode set NORM 0>I/O port set to TTYA. 0>Start Selftest..... 0>CPUs present in system: 0 1 0>Test CPU(s)..... 0>Init SB 0>Initialize I2C Controller 0>Init CPU 0>DMMU 0>DMMU TLB DATA RAM Access 0>DMMU TLB TAGS Access 0>IMMU Registers Access 0>IMMU TLB DATA RAM Access 0>IMMU TLB TAGS Access 0>Init mmu regs 0>Setup L2 Cache 0>L2 Cache Control = 00000000.00f04400 0> Size = 00000000.00100000... 0>L2 Cache Tags Test 0>Scrub and Setup L2 Cache 0>Setup and Enable DMMU 0>Setup DMMU Miss Handler 0>Test Mailbox 0>Scrub Mailbox 0>CPU Tick and Tick Compare Registers Test 0>CPU Stick and Stick Compare Registers Test 0>Set Timing 0> UltraSPARC[TM] IIIi, Version 3.4 1>Init CPU 1> UltraSPARC[TM] IIIi, Version 3.4 1>DMMU 1>DMMU TLB DATA RAM Access 1>DMMU TLB TAGS Access 1>IMMU Registers Access 1>IMMU TLB DATA RAM Access 1>IMMU TLB TAGS Access 1>Init mmu regs 1>Setup L2 Cache 1>L2 Cache Control = 00000000.00f04400 1> Size = 00000000.00100000... 1>L2 Cache Tags Test 1>Scrub and Setup L2 Cache 1>Setup and Enable DMMU 1>Setup DMMU Miss Handler 1>Test Mailbox 1>Scrub Mailbox 1>CPU Tick and Tick Compare Registers Test 1>CPU Stick and Stick Compare Registers Test 0>Interrupt Crosscall..... 1>Setup Int Handlers 0>Setup Int Handlers 0>Send Int CPU 1 1>Send Int to Master CPU 0>MB: Part-Dash-Rev#: 3753346-04-50 Serial#: SD05LH 0>CPU0 MB/P0/B0/D0: 0>Part#: 72D64300GBR6C Serial#: 010cab13 Date Code: 0627 Rev#: 036d 0>CPU0 MB/P0/B0/D1: 0>Part#: 72D64300GBR6C Serial#: 010cab12 Date Code: 0627 Rev#: 036d 0>CPU1 MB/P1/B0/D0: 0>Part#: 72D64300GBR6C Serial#: 010cab14 Date Code: 0627 Rev#: 036d 0>CPU1 MB/P1/B0/D1: 0>Part#: 72D64300GBR6C Serial#: 010cae14 Date Code: 0627 Rev#: 036d 0>Set CPU/System Speed 0>Jumper data = 3a 0>.. 0>Send MC Timing CPU 1 0>Init Memory..... 0>Probe Dimms 1>Probe Dimms 1>Init Mem Controller Regs 0>Init Mem Controller Regs 1>Set JBUS config reg 0>Set JBUS config reg 0>IO-Bridge unit 0 init test 0>IO-Bridge unit 1 init test 0>Do PLL reset 0>Setting timing to 9:1 12:1, system frequency 167 MHz, CPU frequency 1503 MHz 0>Soft Power-on RST thru SW 0>PLL Reset..... 0>Init SB 0>Initialize I2C Controller 0>Init CPU 0>Init mmu regs 0>Setup L2 Cache 0>L2 Cache Control = 00000000.00f04400 0> Size = 00000000.00100000... 0>Setup and Enable DMMU 0>Setup DMMU Miss Handler 0>Scrub Mailbox 0>Timing is 9:1 12:1, sys 167 MHz, CPU 1504 MHz, mem 125 MHz. 0> UltraSPARC[TM] IIIi, Version 3.4 1>Init CPU 1> UltraSPARC[TM] IIIi, Version 3.4 1>Init mmu regs 1>Setup L2 Cache 1>L2 Cache Control = 00000000.00f04400 1> Size = 00000000.00100000... 1>Setup and Enable DMMU 1>Setup DMMU Miss Handler 1>Scrub Mailbox 1>Timing is 9:1 12:1, sys 167 MHz, CPU 1504 MHz, mem 125 MHz. 0>Init Memory..... 0>Probe Dimms 1>Probe Dimms 1>Init Mem Controller Sequence 0>Init Mem Controller Sequence 0>IO-Bridge unit 0 init test 0>IO-Bridge unit 1 init test 0>Test Memory..... 0>Select Bank Config 0>Probe and Setup Memory 0>INFO: 1024MB Bank 0, Dimm Type X4 0>INFO: No memory detected in Bank 1 0>INFO: No memory detected in Bank 2 0>INFO: No memory detected in Bank 3 0> 0>Data Bitwalk on Master 0> Test Bank 0. 0>Address Bitwalk on Master 0>Addr walk mem test on CPU 0 Bank 0: 00000000.00000000 to 00000000.40000000. 0>Set Mailbox 0>Final mc1 is 10000006.3e581c5b. 0>Setup Final DMMU Entries 0>Post Image Region Scrub 0>Run POST from Memory 0>Verifying checksum on copied image. 0>The Memory's CHECKSUM value is a2e5. 0>The Memory's Content Size value is 81679. 0>Success... Checksum on Memory Validated. 1>Select Bank Config 1>Probe and Setup Memory 1>INFO: 1024MB Bank 0, Dimm Type X4 1>INFO: No memory detected in Bank 1 1>INFO: No memory detected in Bank 2 1>INFO: No memory detected in Bank 3 1> 1>Set Mailbox 1>Final mc1 is 10000006.3e581c5b. 0>Data Bitwalk on Slave 1 0> Test Bank 0. 0>Address Bitwalk on Slave 1 0>Addr walk mem test on CPU 1 Bank 0: 00000010.00000000 to 00000010.40000000. 1>Setup Final DMMU Entries 1>Map Slave POST to master memory 0>Test CPU Caches..... 1>I-Cache RAM Test 0>I-Cache RAM Test 1>I-Cache Tag RAM 0>I-Cache Tag RAM 1>I-Cache Valid/Predict TAGS Test 0>I-Cache Valid/Predict TAGS Test 1>I-Cache Snoop Tag Field 0>I-Cache Snoop Tag Field 1>I-Cache Branch Predict Array Test 0>I-Cache Branch Predict Array Test 1>Branch Prediction Initialization 0>Branch Prediction Initialization 1>D-Cache RAM 0>D-Cache RAM 1>D-Cache Tags 0>D-Cache Tags 1>D-Cache Micro Tags 0>D-Cache Micro Tags 1>D-Cache SnoopTags Test 0>D-Cache SnoopTags Test 1>W-Cache RAM 0>W-Cache RAM 1>W-Cache Tags 0>W-Cache Tags 1>W-Cache Valid bit Test 0>W-Cache Valid bit Test 1>W-Cache Bank valid bit Test 0>W-Cache Bank valid bit Test 1>W-Cache SnoopTAGS Test 0>W-Cache SnoopTAGS Test 1>P-Cache RAM 0>P-Cache RAM 1>P-Cache Tags 0>P-Cache Tags 1>P-Cache SnoopTags Test 0>P-Cache SnoopTags Test 1>P-Cache Status Data Test 0>P-Cache Status Data Test 1>8k DMMU TLB 0 Data 0>8k DMMU TLB 0 Data 1>8k DMMU TLB 1 Data 0>8k DMMU TLB 1 Data 1>8k DMMU TLB 0 Tags 0>8k DMMU TLB 0 Tags 1>8k DMMU TLB 1 Tags 0>8k DMMU TLB 1 Tags 1>8k IMMU TLB Data 0>8k IMMU TLB Data 1>8k IMMU TLB Tags 0>8k IMMU TLB Tags 1>FPU Registers and Data Path 0>FPU Registers and Data Path 1>FPU Move Registers 0>FPU Move Registers 1>FSR Read/Write 0>FSR Read/Write 1>FPU Block Register Test 0>FPU Block Register Test 1>FPU Branch Instructions 0>FPU Branch Instructions 1>FPU Functional Test 0>FPU Functional Test 1>Scrub Memory 0>Scrub Memory 1>Flush Caches 0>Flush Caches 1>L2-Cache Functional 0>Functional CPU Tests..... 0>L2-Cache Functional 1>L2-Cache Stress 0>L2-Cache Stress 1>IMMU Functional 0>IMMU Functional 1>DMMU Functional 0>DMMU Functional 1>I-Cache Functional 0>I-Cache Functional 1>I-Cache Parity Functional 0>I-Cache Parity Functional 1>I-Cache Parity Tag 0>I-Cache Parity Tag 1>I-Cache Snoop Parity Tag 0>I-Cache Snoop Parity Tag 1>D-Cache Functional 0>D-Cache Functional 1>D-Cache Parity Functional 0>D-Cache Parity Functional 1>D-Cache Parity Tag Test 0>D-Cache Parity Tag Test 1>W-Cache Functional 0>W-Cache Functional 1>Graphics Functional 1>CPU Superscalar Dispatch 0>Graphics Functional 0>CPU Superscalar Dispatch 1>SPARC Atomic Instruction Test 0>SPARC Atomic Instruction Test 1>Non SPARC Atomic Instruction Test 0>Non SPARC Atomic Instruction Test 1>SOFTINT Register and Interrupt Test 1>Branch Memory Test 0>SOFTINT Register and Interrupt Test 1>Fast ECC test 0>Branch Memory Test 1>System ECC test 0>Fast ECC test 0>System ECC test 0>XBus SRAM 0>IO-Bridge SouthBridge Remap Devs 0>IO-Bridge Tests..... 0>JBUS quick check 0> to IO-bridge_0 0> to IO-bridge_1 0>IO-Bridge unit 0 sram test 0>IO-Bridge unit 0 reg test 0>IO-Bridge unit 0 mem test 0>IO-Bridge unit 0 PCI id test 0>IO-Bridge unit 0 interrupt test 0>IO-Bridge unit 1 sram test 0>IO-Bridge unit 1 reg test 0>IO-Bridge unit 1 mem test 0>IO-Bridge unit 1 PCI id test 0>IO-Bridge unit 1 interrupt test 0>IO-Bridge unit 0 init test 1>IO-Bridge unit 0 sram test 1>IO-Bridge unit 0 reg test 1>IO-Bridge unit 0 mem test 1>IO-Bridge unit 0 PCI id test 1>IO-Bridge unit 0 interrupt test 1>IO-Bridge unit 1 init test 1>IO-Bridge unit 1 sram test 1>IO-Bridge unit 1 reg test 1>IO-Bridge unit 1 mem test 1>IO-Bridge unit 1 PCI id test 1>IO-Bridge unit 1 interrupt test 1>Print Mem Config 1>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON. 1>Memory interleave set to 0 1> Bank 0 1024MB : 00000010.00000000 -> 00000010.40000000. 0>Print Mem Config 0>Caches : Icache is ON, Dcache is ON, Wcache is ON, Pcache is ON. 0>Memory interleave set to 0 0> Bank 0 1024MB : 00000000.00000000 -> 00000000.40000000. 1>Block Memory 0>Block Memory 1>Test 1073741824 bytes on bank 0.... 0>Test 1067450368 bytes on bank 0.... 0>0% Done... 0>2% Done... 0>3% Done... 0>4% Done... 0>6% Done... 0>7% Done... 0>9% Done... 0>10% Done... 0>11% Done... 0>13% Done... 0>14% Done... 0>16% Done... 0>17% Done... 0>18% Done... 0>20% Done... 0>21% Done... 0>22% Done... 0>24% Done... 0>25% Done... 0>27% Done... 0>28% Done... 0>29% Done... 0>31% Done... 0>32% Done... 0>34% Done... 0>35% Done... 0>36% Done... 0>38% Done... 0>39% Done... 0>41% Done... 0>42% Done... 0>43% Done... 0>45% Done... 0>46% Done... 0>48% Done... 0>49% Done... 0>50% Done... 0>52% Done... 0>53% Done... 0>55% Done... 0>56% Done... 0>57% Done... 0>59% Done... 0>60% Done... 0>62% Done... 0>63% Done... 0>64% Done... 0>66% Done... 0>67% Done... 0>69% Done... 0>70% Done... 0>71% Done... 0>73% Done... 0>74% Done... 0>76% Done... 0>77% Done... 0>78% Done... 0>80% Done... 0>81% Done... 0>83% Done... 0>84% Done... 0>85% Done... 0>87% Done... 0>88% Done... 0>90% Done... 0>91% Done... 0>92% Done... 0>94% Done... 0>95% Done... 0>97% Done... 0>98% Done... 0>99% Done... 0>INFO: 0> POST Passed all devices. 0> 0>POST: Return to OBP. SC Alert: Host System has Reset NOTICE: Keyswitch set to diagnostic position. @(#)OBP 4.18.10 2006/03/03 13:59 Sun Fire V210/V240,Netra 210/240 Clearing TLBs POST Results: Cpu 0000.0000.0000.0001 %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.4656 %o2 = ffff.ffff.ffff.ffff POST Results: Cpu 0000.0000.0000.0000 %o0 = 0000.0000.0000.0000 %o1 = ffff.ffff.f00a.4656 %o2 = ffff.ffff.ffff.ffff Membase: 0000.0000.0000.0000 MemSize: 0000.0000.0004.0000 Init CPU arrays Done Init E$ tags Done Setup TLB (small-footprint mode) Done MMUs ON Scrubbing Tomatillo tags... 0 1 Find dropin, Copying Done, Size 0000.0000.0000.6e70 PC = 0000.07ff.f000.5d68 PC = 0000.0000.0000.5e18 Find dropin, Copying Done, Size 0000.0000.0001.1bd0 Diagnostic console initialized Configuring system memory & CPU(s) Programming IMAX CPU 0 Memory Configuration: Valid CPU 1 Memory Configuration: Valid CPU 0 Bank 0 1024 MB Bank 1 Bank 2 Bank 3 CPU 1 Bank 0 1024 MB Bank 1 Bank 2 Bank 3 NOTICE: Keyswitch set to diagnostic position. @(#)OBP 4.18.10 2006/03/03 13:59 Sun Fire V210/V240,Netra 210/240 Clearing TLBs Loading Configuration Membase: 0000.0010.0000.0000 MemSize: 0000.0000.4000.0000 Init CPU arrays Done Init E$ tags Done Setup TLB Done MMUs ON Scrubbing Tomatillo tags... 0 1 Block Scrubbing Done Find dropin, Copying Done, Size 0000.0000.0000.6e70 PC = 0000.07ff.f000.5d68 PC = 0000.0000.0000.5e18 Find dropin, (copied), Decompressing Done, Size 0000.0000.0006.95c0 Diagnostic console initialized System Reset: CPU Reset (SPOR) Programming IMAX Probing system devices jbus at 0,0 SUNW,UltraSPARC-IIIi (1503 MHz @ 9:1, 1 MB) memory-controller jbus at 1,0 SUNW,UltraSPARC-IIIi (1503 MHz @ 9:1, 1 MB) memory-controller jbus at 1f,0 pci jbus at 1e,0 pci jbus at 1c,0 pci jbus at 1d,0 pci Loading Support Packages: kbd-translator obp-tftp SUNW,i2c-ram-device SUNW,fru-device SUNW,asr Loading onboard drivers: /pci@1e,600000: Device 7 isa /pci@1e,600000/isa@7: flashprom rtc i2c power serial serial serial rmc-comm /pci@1e,600000/isa@7/i2c@0,320: i2c-bridge i2c-bridge motherboard-fru-prom chassis-fru-prom power-supply-fru-prom power-supply-fru-prom dimm-spd dimm-spd dimm-spd dimm-spd rscrtc nvram idprom gpio gpio gpio gpio gpio gpio Probing memory CPU 0 Bank 0 base 0 size 1024 MB CPU 1 Bank 0 base 1000000000 size 1024 MB Probing I/O buses /pci@1d,700000: Device 2 network network /pci@1f,700000: Device 2 network network /pci@1e,600000: Device 6 pmu i2c gpio /pci@1e,600000/pmu@6/i2c@0,0: /pci@1e,600000: Device a usb /pci@1e,600000: Device d ide disk cdrom /pci@1e,600000: Device 2 Nothing there /pci@1e,600000: Device 3 Nothing there /pci@1c,600000: Device 2 scsi disk tape scsi disk tape /pci@1c,600000: Device 1 Nothing there /pci@1d,700000: Device 1 Nothing there Sun Fire V240, No Keyboard Copyright 2005 Sun Microsystems, Inc. All rights reserved. OpenBoot 4.18.10, 2048 MB memory installed, Serial #72198873. Ethernet address 0:14:4f:4d:aa:d9, Host ID: 844daad9. Running diagnostic script obdiag/normal Testing /pci@1e,600000/ide@d >> Primary interface selected. Subtest pci-config-reg-tests Subtest pci-config-reg-tests:vendor-id-test Subtest pci-config-reg-tests:device-id-test Subtest pci-config-reg-tests:status-reg-test Subtest pci-config-reg-tests:rom-expansion-test Testing /pci@1e,600000/isa@7/rtc@0,70 Subtest rtc-tick-test Testing /pci@1c,600000/scsi@2 >> SCSI registers Subtest scsi-reg-test >> SCSI timers Subtest scsi-timer-test >> SCSI DMA transfer Subtest scsi-dma-test SCSI device BIST tests not run. To run BIST tests include "bist" as a test-arg. Testing /pci@1c,600000/scsi@2,1 >> SCSI registers Subtest scsi-reg-test >> SCSI timers Subtest scsi-timer-test >> SCSI DMA transfer Subtest scsi-dma-test SCSI device BIST tests not run. To run BIST tests include "bist" as a test-arg. Testing /pci@1e,600000/isa@7/serial@0,2e8 Subtest internal-loopback BAUDRATE=115200 >> External Loopback Test not run. To run the test include >> "loopback" in TEST-ARGS and connect external loopback to the device port. Testing /pci@1e,600000/isa@7/serial@0,3f8 >> Port is not tested because it is in use as a console device. System is operating in Service Mode. Initializing 1MB of memory at addr 103feec000 - Initializing 1MB of memory at addr 103fee0000 - Initializing 1MB of memory at addr 103fe96000 - Initializing 15MB of memory at addr 103f000000 - Initializing 1008MB of memory at addr 1000000000 - Initializing 1024MB of memory at addr 0 /- Aborting auto-boot sequence. {1} ok